Peplov Ilya Sergeevich

Place of work

FSAEI of HE "National Research University of Electronic Technology"

Author's articles(2)

RTL design techniques of asynchronous FIFO memory blocks with area and power consumption optimizations



this paper presents several new asynchronous FIFO designs. While most existing FIFO’s have higher throughput for higher latency, our goal is to achieve very low latency while maintaining good throughput. The designs are implemented as circular arrays of cells connected to common data buses. Data items are not moved around the array once; they are enqueued. Each cell’s input and output behavior is dictated by the flow of two tokens around the ring: one that allows enqueuing data and one that allows dequeuing data. Since the problems were found in gray code's nature, both FIFO architectures repr...

Методика автоматизации размещения сигнальных выводов и выводов питания по периметру ядра кристалла или макроблока ИС (в среде инструмента Innovus (Encounter) САПР Cadence)



This article considers the possibility of automating the placement of signal and power pins along the perimeter of the core or a separate macroblock in the IC at the stage of physical synthesis. There is the method of automated placement of conclusions, its rationale and description of the placement algorithm adapted to work with Innovus tool. Also, the result of the algorithm’s work is shown on the example of the real project.